186 MCU extended 24bit adressing

[nobody]

Hi,

just out of curiosity, would NASM support the extended 24bit addressing mode offered by many current 186-compatible microcontrollers (Turbo186, V186, RDC, PixelWorks, Lantronix/GridConnect DSTni-LX & -EX, ...)?

Basically, the Segment of a Segment:Offset pair is not shifted by 4, but 8 bits, before arriving at the physical location; typically, the MCU can be booted in either 20 and 24 bit modes (supporting 1M / 16 M max), by hardwiring a certain pin during power-on to Gnd...

The primitive method would probably be to create a Macro to shift the segment of an automatically calculated address by 4 bits, or manually hardcode any far calls...

Best regards,
   Richard

[nobody]

Does NASM actually require any changes for this?

The BIN format doesn't support segment base references,
and the linkable formats require support in the linker, not
the assembler. Also, a quick glance over the NASM source
for >>4 and <<4 doesn't yield obvious candidates.