gdt:; offset 0x0 (0 bytes).null_descriptor: dq 0x0; offset 0x8 (8 bytes).code_descriptor: ; cs should point to this descriptor dw 0xffff ; segment limit first 0-15 bits dw 0x0 ; base first 0-15 bits db 0x0 ; base 16-23 bits db 0x9a ; access byte db 0b11001111 ; high 4 bits (flags) low 4 bits (limit 4 last bits)(limit is 20 bit wide) db 0x0 ; base 24-31 bits; offset 0x10 (16 bytes).data_descriptor: ; ds, es, fs, gs, and ss should point to this descriptor dw 0xffff ; segment limit first 0-15 bits dw 0x0 ; base first 0-15 bits db 0x0 ; base 16-23 bits db 0x92 ; access byte db 0b11001111 ; high 4 bits (flags) low 4 bits (limit 4 last bits)(limit is 20 bit wide) db 0x0 ; base 24-31 bits
It's to do with endianism. Intel processors use Little Endian addressing, so the least significant byte is stored at the highest address. So the diagram is right, just not necessarily logical.