Author Topic: Checking TLB  (Read 6454 times)


  • Guest
Checking TLB
« on: February 09, 2005, 11:34:06 AM »
Hi!I am trying to check Translation Lookaside Buffer.I have activated paging and i can't see any hit.Is there any extra bit to activate TLB,or something new for Pentium4(this methodology is from Pentium manual)??Here is the code i am using for searching...

mov ebx,3  ; data TLB and read
next:mov eax,ebx
       mov ecx,08h ; TR6 <= eax
       mov ecx,09h ; eax <= TR7
       shr eax,4 ; eax[0] <= hit_bit
       and al,1
       jnz hit_print ; print a hit message
       cmp ebx,0fffff003 ; for all linear addresses
       jz end
       add ebx,1000h
       jmp next


  • Guest
Re: Checking TLB
« Reply #1 on: February 10, 2005, 02:31:55 AM »
MSRs 0000_0008h and 0000_0009h are
specific to the P5 core -- they are not
valid for the P6 or P4 core.

However, you can make TLB hits/misses
visible without relying on implementation-
specific x86 functionality.

Just access a page, clear its A/D bits in
memory, and access it again. If the page
is still in the TLB, then the A/D bits won't
get set again. By contrast, if the TLB no
longer holds that page, the resulting TLB
fill will set the A/D bits again.

I once wrote a TLB-sizing/stressing test
which fit into a single 4 KB page -- code,
data, and as large a page table as there
was room left (in my case: 2 KB code and
data, and 2 KB page table). In essence it
mapped that single page throughout the
address space, walked all of those pages
via reads/writes/fetches, cleared the A/D
bits, walked the pages again, and finally
took another look at the A/D bits.