I have written some makefiles to compile my C-code, but now I also want to compile my assembly code wit autogenerated depedencies in my makefiles.
This could be easy if the build dir would also be the src dir, but this isn´t the case. For my C-code I use a makefile like this:
CXXFLAGS = ...
LDFLAGS = ...
PREFIX = ../src/
SRCS = foo.cpp bar.cpp
OBJS = $(SRCS:%.cpp=%.o)
DEPENDFILE = .depend
VPATH = $(PREFIX)
.PHONY: all clean
all: $(DEPENDFILE) final.file
$(DEPENDFILE): $(SRCS:%=$(PREFIX)%)
$(CXX) -M $(SRCS:%=$(PREFIX)%) $(CXXFLAGS) > $(DEPENDFILE)
-include $(DEPENDFILE)
final.file: $(OBJS)
$(LD) $(OBJS) -o final.file $(LDFLAGS)
clean:
...
I also like to use a makefile like this for my assembly files. But this won´t work, because nasm does not the same as gcc with the generated dependencies. I assume the following (taken from gcc´s documentation):
-M
...
Unless specified explicitly (with -MT or -MQ), the object file name consists of the name of the source file with any suffix replaced with object file suffix and with any leading directory parts removed. If there are many included files then the rule is split into several lines using `\'-newline. The rule has no commands.
But nasm does not remove the leading directory parts. So how can I solve this.
As I didn´t get this far, I couldn´t try for myself. So how does make know which program to call to compile an assembly file?
