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91
Programming with NASM / Re: Macro to find nearest return instruction
« Last post by zcap on June 28, 2022, 11:27:32 PM »
Think I solved it, though predictably, it works by looking backwards in the file for the previous ret instruction.
This seemed to produce the deisred output in the listing file:


%macro return 0
%%_ret:
    ret
%assign retOff %%_ret-$$  ;Get offset into segment of %%_ret
%endmacro

%macro cret 1
%%_base:
%assign baseVar %%_base-$$ ;Get offset into segment of %%_base
    %ifdef retOff
    %if (baseVar - retOff <= 126) && (baseVar > retOff)
    j%+1 short (retOff+section.<currentSegment>.vstart)
    %else
    j%-1 short %%a
    return
%%a:
    %endif
    %else
    j%-1 short %%a
    return
%%a:
    %endif
%endmacro


section.<currentSegment>.vstart is needed in multi segment programs which use segment relocation at runtime as the offsets are worked out relative to the file it seems and not their loacations in memory. I am now trying to work out how to "dynamically" work out the current segment and get that segment's virtual start address. In any case, for most tasks, it is not needed.

Comments and suggestions are welcome!
92
Programming with NASM / Macro to find nearest return instruction
« Last post by zcap on June 28, 2022, 10:24:52 PM »
Hi all.

I was wondering if it is at all possible to use the NASM macro language to find the "nearest" RET instructions to a particular address? For example, I frequently use simple conditional return macros but in some cases, where there might be multiple conditional return macros within a 128 byte window of a ret instruction, I'd rather not have each conditional return macro define it's own ret instruction, but instead have them share the same return instruction.
As part of my conditional return macros, I have a "return" macro which wraps the ret instruction and adds a label which points to the instruction. This label is called %%_ret.
My idea is to search the 128 byte window for a regular expression which ends with a _ret label, from $ inside the conditional return macro, but I am not sure if the NASM preprocessor accept's regexes. Nevertheless, I thought I'd ask here. Perhaps I am approaching it the wrong way.
Either way, any help would be appreciated.

Many thanks,
zcap

PS. Here is an example of the situation:
   
myProc:
    call proc1
    retc    ;Return if carry
    push rax
    movzx eax, word [var1]
    cmp ax, word [rdi + myStruc.localLabel1]
    pop rax
    rete
    mov al, 6
    stc
    return


Here are my macro definitions for the retc, rete and return macros:

%macro return 0
%%_ret:
    ret
%endmacro

%macro cret 1
    j%-1 short %%a
    return
%%a:
%endmacro

%macro retc 0
cret c
%endmacro

%macro rete 0
cret e
%endmacro

93
Programming with NASM / Re: Changing entry of Interrupt Vector Table
« Last post by debs3759 on June 19, 2022, 07:32:15 PM »
From nasmdocs 0.98:

Code: [Select]
B.4.127 IRET , IRETW , IRETD : Return from Interrupt
        IRET ; CF [8086]
        IRETW ; o16 CF [8086]
        IRETD ; o32 CF [386]
IRET returns from an interrupt (hardware or software) by means of popping IP (or EIP ), CS and
the flags off the stack and then continuing execution from the new CS:IP .
IRETW pops IP , CS and the flags as 2 bytes each, taking 6 bytes off the stack in total. IRETD pops
EIP as 4 bytes, pops a further 4 bytes of which the top two are discarded and the bottom two go
into CS , and pops the flags as 4 bytes as well, taking 12 bytes off the stack.
IRET is a shorthand for either IRETW or IRETD , depending on the default BITS setting at the time.

So to return to a different address, you need to change the address stored on the stack.
94
Programming with NASM / Re: Changing entry of Interrupt Vector Table
« Last post by patdes20 on June 19, 2022, 03:51:08 PM »
Hi everyone, I just have one further question: How do I return to a different address with the interrupt return. I want to change the executed function every 55ms. Can I just pop the stack and push a different address or does iret put more information on the stack?
95
Using NASM / Re: AESDEC with x64
« Last post by fredericopissarra on June 14, 2022, 04:13:30 PM »
Probably NOT... You don't need to use CPU directive, unless you want to LIMIT the instruction set.
96
Using NASM / Re: AESDEC with x64
« Last post by RomekAtomek on June 14, 2022, 12:39:01 PM »
My mistake was that I made the assumption that IA64 only applies to itanium.


I have another question. Is AESDEC instruction available in 16b mode? NASM accept it.

  1020                                  CPU IA64
  1021                                  BITS 16           
  1022 00000CEA C4E269DFCB                       VAESDECLAST XMM1, XMM2, XMM3
  1023 00000CEF 660F38DECA                       AESDEC XMM1, XMM2

97
Using NASM / Re: AESDEC with x64
« Last post by fredericopissarra on June 14, 2022, 10:25:13 AM »
It was introduced with the Westmere architecture. If none of your hardware is x64 capable, it won't be supported.
The problem, above, is the CPU directive...
Code: [Select]
$ cat test.asm
  bits 64
  ; cpu x64

  aesdec xmm1,xmm2

$ nasm -v
NASM version 2.15.05 compiled on Oct 24 2020

$ nasm -l test.lst test.asm
$
Code: [Select]
1                      bits  64
2                      ;cpu x64
3                     
4 00000000 660F38DECA  aesdec xmm1,xmm2
Code: [Select]
$ cat test2.asm
  bits 64
  cpu x64

  aesdec xmm1,xmm2

$ nasm -l test2.lst test2.asm
test2.asm:4: error: no instruction for this cpu level
From the docs:
Quote
The CPU directive restricts assembly to those instructions which are available on the specified CPU
Without CPU there are no restrictions.
98
Hi  lord_raven,

I haven't written a compiler, so I can't help you much.

Nasm doesn't really like your code. Throws a warning right on the first line. Not a good start, I'd say. We can configure Nasm to not emit the warning, but that's not what I think you should do. Your compiler ought to produce code that Nasm likes, I think. There are some things that Nasm doesn't complain about, but which I don't understand. Loading a register with a value and then loading the same register with a different value. You do this in a few places. I don't ;npw what your compiler intends... but then, I haven't written a compiler.

I wish you luck with your project. I hope you don't get too frustrated with it.

Best,
Frank
99
Using NASM / Re: AESDEC with x64
« Last post by debs3759 on June 13, 2022, 10:53:51 PM »
It was introduced with the Westmere architecture. If none of your hardware is x64 capable, it won't be supported.
100
Using NASM / Re: AESDEC with x64
« Last post by fredericopissarra on June 13, 2022, 10:25:08 PM »
nasm doc section 7.11
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