NASM - The Netwide Assembler
NASM Forum => Programming with NASM => Topic started by: elios on October 22, 2012, 12:56:12 AM
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I have a nasm file with this code snippet below. When I assemble it (nasm -f elf -o obj/x86/loader.o src/arch/archx86/loader.asm) I see this warning repeated probably 200 times consecutively:
src/arch/archx86/loader.asm:68: warning: attempt to initialize memory in BSS section `.bss': ignored
src/arch/archx86/loader.asm:68: warning: attempt to initialize memory in BSS section `.bss': ignored
src/arch/archx86/loader.asm:68: warning: attempt to initialize memory in BSS section `.bss': ignored
...
Source snippet:
GLOBAL Interrupts_GetISRPtr ; Address of the kernel main interrupt service routine
GLOBAL MemDefaultISR ; Address of the ISR
SECTION .text
align 4
STACKSIZE equ 0x4000 ; 16k stack size.
PDTSIZE equ 0x400000 ; Size of Paging Table
ISRPTRSIZE equ 0x4 ; Size of ISR Pointer
Paging_GetBaseAddress: ;Get the base address of the Paging Table
mov eax, paging
ret
Interrupts_GetISRPtr:
mov eax, MemDefaultISR
ret
section .bss
stack:
align 0x4
resb STACKSIZE ; Reserve 16k stack on a doubleword boundary
MemDefaultISR:
align 0x4
resb ISRPTRSIZE
paging: ; Reserve space for Paging Tables
align 0x1000
resb PDTSIZE
----- However: If I interchange the last two variables, everything assembles just fine. Could this be a bug? and Should I not worry about that warning?
This works:
section .bss
stack:
align 0x4
resb STACKSIZE ; Reserve 16k stack on a doubleword boundary
paging: ; Reserve space for Paging Tables
align 0x1000
resb PDTSIZE
MemDefaultISR:
align 0x4
resb ISRPTRSIZE
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What version of Nasm are you using?
I seem to recall a bug with the align directive in older versions of Nasm.
That "may" be the cause of your issue although I'm not sure yet...
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I'm using NASM version 2.10.05 compiled on Sep 11 2012
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Sure looks like a bug to me! And a rather strange one, too! Stranger still, I get the same result from nasm-0.98.39!
Just to make it easier to "cut-and-past", I'll put it in "code tags" - with minor "debugging changes".
GLOBAL Interrupts_GetISRPtr ; Address of the kernel main interrupt service routine
GLOBAL MemDefaultISR ; Address of the ISR
SECTION .text
align 4
STACKSIZE equ 0x4000 ; 16k stack size.
PDTSIZE equ 0x400000 ; Size of Paging Table
ISRPTRSIZE equ 0x4 ; Size of ISR Pointer
Paging_GetBaseAddress: ;Get the base address of the Paging Table
mov eax, paging
ret
Interrupts_GetISRPtr:
mov eax, MemDefaultISR
ret
nop
nop
nop
nop
mov eax, endbss
section .bss
stack:
align 0x4
resb STACKSIZE ; Reserve 16k stack on a doubleword boundary
;paging: ; Reserve space for Paging Tables
; align 0x1000
; resb PDTSIZE
MemDefaultISR:
align 0x4
resb ISRPTRSIZE
paging: ; Reserve space for Paging Tables
align 0x1000
resb PDTSIZE
endbss:
My "endbss" label does not come out in the same place, so I suspect that it may NOT be safe to ignore this "warning"! This may take some research, bear with us. Thanks for the feedback, elios!
Best,
Frank
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Doesn't seem like a bug to me.
When you rearrange your variables and their respective alignments, you happen to have alignments that are factors of the previous resb, or object file section alignment, for which align will be optimized away, i.e. ignored, thus placating any warnings.
Your original arrangement triggers an actual alignment (resb 4 followed by align 0x1000) thus issuing those warnings.
The alignment directive you'd want to use in the BSS section is alignb.
More about align and alignb: http://www.nasm.us/xdoc/2.10.05/html/nasmdoc4.html#section-4.12.12 (http://www.nasm.us/xdoc/2.10.05/html/nasmdoc4.html#section-4.12.12)
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Confirmed. Thanks, Keith! Whew!
Best,
Frank
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Thanks for the info!