NASM - The Netwide Assembler
NASM Forum => Using NASM => Topic started by: nobody on January 15, 2009, 03:34:45 AM
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Hi,
Anyone know what the CL stands for in the last four lines of the doc
for the SHLD/SHRD instruction below? The shift count is a parameter
to a function I'm writing and I'm not sure how I'm going to get it into
the instruction when all you can use is immed8 and CL.
Michael
SHLD/SHRD - Double Precision Shift (386+)
Usage: SHLD dest,src,count
SHRD dest,src,count
Modifies flags: CF PF SF ZF (OF,AF undefined)
SHLD shifts dest to the left count times and the bit positions
opened are filled with the most significant bits of src. SHRD
shifts dest to the right count times and the bit positions
opened are filled with the least significant bits of the second
operand. Only the 5 lower bits of count are used.
Clocks Size
Operands 808x 286 386 486 Bytes
reg16,reg16,immed8 - - 3 2 4
reg32,reg32,immed8 - - 3 2 4
mem16,reg16,immed8 - - 7 3 6
mem32,reg32,immed8 - - 7 3 6
reg16,reg16,CL - - 3 3 3
reg32,reg32,CL - - 3 3 3
mem16,reg16,CL - - 7 4 5
mem32,reg32,CL - - 7 4 5
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The cl register - low 8 bits of ecx.
...
mov ecx, [ebp + ???] ; address of shrd count
mov cl, [ecx]
shrd eax, edx, cl
...
That what you mean?
Best,
Frank
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Hi Frank,
Once again I guessed right, just after I posted, but thanks for the confirmation.
The count is going to be in the low end of a 64-bit integer, so could I just
mov ecx, [ecx]
or must I use the CL notation?
Michael